The present invention relates to a universal device for coupling a computer bus to a controller of a group of peripherals, which are connected to one another by a specific link to which the controller is physically connected. More particularly, it is applicable to a group of peripherals or terminals that are connected to one another via an FDDI-type of ring network for data transmission, whose transmission carrier is constituted by optical fibers. It is also applicable to a group of peripherals connected to one another by a link characteristic to them, such as an SCSI-type link that connects magnetic disk memories.
Data transmission networks that use fiber optics as transmission carriers are used increasingly often and are defined in their broad outlines in the publications developed in such international standardization committees as the American National Standards Institute (ANSI), under reference number X3T9-5. These standards defined by ANSI have also been adopted by ISO, the International Standards Organization. This standard defines a set of physical and electrical characteristics of the network, such as the maximum total length of the fiber, the maximum distance between stations of a network, and the code in which the information is written and transmitted from one station to another. One of the numerous advantages of using fiber optics in the networks is the increased transmission rate obtained, which in on the order of 100 megabits per second.
SCSI-type links have also been defined by standards, both by ANSI and by ISO.
It is known that in a network, the information messages sent by the various stations are constituted by a plurality of frames. Hence the frame is the individual message and is structured; it includes messages marking the start and end, respectively; synchronization signals, from which the clock can be deduced; the address of the station to which a message is addressed; the address of the sending station; the length of the data; the useful data; and so forth. More simply, a frame can be said to be made up of useful data, are framed in time by signals placed at the head and foot of the frame. The signals at the head and foot of the frame that frame the useful data are called "command characters".
It is also known that the set of constituent functional elements of a computer, whether they are processors constituting it (central processing unity or input/output processors), random access and read only memories, input/output controllers or peripheral controllers, are disposed on a set of boards of standardized dimensions. These boards are generally connected to the same parallel-type bus, assuring communication among the various processors, data transport between the boards, and the electrical supply to the boards.
The bus commonly known as the Multibus II (trademark filed by the Intel Corporation) is one of the most often used buses. Its architecture is structured around a main bus of the parallel type, which is standardized to the IEEE (Institute of Electrical and Electronic Engineers) Standard 1296, and is commonly known as PSB (for parallel system bus).
One such computer bus is connected to this specific link (FDDI network or SCSI link) by way of a gateway connection device, whose function is to adapt the information transmission conditions on the Multibus II to the transmission conditions on the network or in the characteristic link connecting the peripherals. In fact, the data transmission modes on the PSB bus on the one hand and on the network (such as FDDI) on the other are completely different, both as to the information transmission rate and as to the transmission particles used, the writing codes, the information, the format, the control characters, the information transmission (parallel on the Multibus II, serial on the FDDI network), and so forth.
FIGS. 1A and 1B, respectively, show the general structure of such a gateway device, when the transmission network is the FDDI type, and when the characteristic link is the SCSI type.
Turning to FIG. 1A:
This shows a computer ORD, whose various constituent elements are disposed on a plurality of boards C communicating with one another by way of a bus PSB. Each board C is connected to PSB by way of an MPC coprocessor, for example an Intel VL 82c389, and communicates by message mode with the other constituent functional elements of the computer. This mode of communications between the various boards of ORD is defined precisely in aforementioned IEEE Standard 1296.
The computer ORD is connected to a network RN, in the form of a ring, of the FDDI type, by way of the gateway connection device DPC. The network RN is made up of a main ring AP and a secondary ring AS.
The device DPC is composed on the one hand of a universal coupling device GPU (for general purpose unit), an adaptor device DEA, and an interface IHA assuring the transfer of information between the universal coupling device GPU and the adaptor device DEA.
The universal coupling device GPU is connected to PSB via a coprocessor MPC, of the same type as the coprocessors of the boards C of the computer ORD.
The device DPC is physically connected to the network RN by way of a physical network access device, DAP, which belongs to the adaptor device DEA.
In FIG. 1B, the gateway connection device DPC has the same structure as in FIG. 1A; the difference is that the adaptor device DEA is connected by way of a physical adaptation device DAP to a link of the SCSI type, to which the respective disk memories D.sub.1, . . . , D.sub.i, . . . , D.sub.j, . . . , D.sub.n are connected.
Both in FIG. 1A and in FIG. 1B, the device DPC may be embodied by either one and the same board or by two separate boards, depending on the importance of the elements making up each of the constituents of this device, that is, GPU and DEA.
The general structure of the device DPC shown in FIGS. 1A and 1B, and embodiments and the function of the two elements constituting it, that is, GPU and DEA, are described in French Patent Application 89 10 156 filed on Jul. 27, 1989 by the present Applicant, entitled "Dispositif passerelle de connexion d'un bus d'ordinateur a un reseau fibre optique en forme d'anneau" corresponding to U.S. application Ser. No. 07/557,519, filed Jul. 4, 1990, entitled "Gateway Device for Connecting a Computer Bus to a Fiber-optic Token-ring Network". The subject matter of said U.S. application is hereby incorporated by reference.
The invention essentially relates to the universal coupling device GPU; the essential constituent elements of the universal coupling device GPUA that are used in the device DPC described in the aforementioned patent application will be recalled by reference to FIG. 2; this device accordingly constitutes a prior art way of embodying such a universal coupling device.
As can be seen from this same FIG. 2, the device GPUA is constructed around a microprocessor CPU and a bus BH associated with the microprocessor. It also includes a programmable read-only memory MM and a random access memory MV, and a direct memory access controller of the DMA type, represented by the symbol DMAC, for the random access memory MV.
In addition, the transfer interface IHA connected to the universal device GPUA by way of the bus BH includes an interface IHAD enabling the transfer of the useful data from or to GPUA and a transfer interface for the control blocks, including the command characters of the frames received or sent, that is, IHAC enabling the transfer of the control blocks from or to GPUA.
If one seeks to send information from the computer ORD to the network RN via PSB, then one proceeds as follows:
This information is transmitted via the coprocessor MPC and then memorized in the memory MV, and then analyzed by the microprocessor CPU, which processes a control block SCB containing parameters relating to the constitution of the FDDI-type frames, on the one hand, which are intended to be sent over the network RN (command characters), and on the other, relating to the nature of the operations to be performed by DEA. For example, these parameters are the address of the addressee of the information, the address of the sender, the length of the messages that are sent, and so forth.
As soon as CPU has constituted SCB, the latter is then sent, as are the data corresponding to it, over the bus BH to the interface IHA; SCB is routed to IHAC, while the data are routed to IHAD. The control block SCB is for example routed over 16 bits, that is, HC.sub.0 through HC.sub.15, accompanied by two parity bits HCP.sub.0 and HCP.sub.1. As for the data, they are routed over 32 bits, that is, HD.sub.0 through HD.sub.31, accompanied by four parity bits HDP.sub.0 through HDP.sub.3.
Both the data and the command block SCB are temporarily stored in their respective interfaces IHAC and IHAD before being transferred over the bus BC and BDF, respectively, which belong to the adaptor device DEA.
It is suitable to note that the transfer of the control blocks and data over the two separate buses BC and BDF is done independently for one and the other. The way in which the information is transferred and stored, before being sent over the network RN, via the adaptor device DEA is described in detail in the aforementioned French patent application.
The disadvantage of the universal coupling device GPUA is that the microprocessor has only one and the same bus at its disposal to perform the transfer of the useful data, the transfer of the data necessary for the running of its own code, and finally the data necessary for management of the protocols used on the bus PSB and in the network FDDI, respectively. It is not possible to make the best use of the microprocessor performance, because it is limited by the existence of only one bus.
The present invention makes it possible to overcome these disadvantages, by providing a double-port video RAM memory between the interface IHAD and the coprocessor MPC, in which memory the useful data of the FDDI (or SCSI) frames are temporarily stored before being transferred to the coprocessor MPC under the control of a controller of the DMA type. In addition, the microprocessor can use its internal bus specifically for running its own code, that is, for the data necessary for its operating system, and finally for managing protocols. The data can accordingly be transferred while at the same time work is done on the adaptation of the protocols, or while the operating system operations are being performed.
According to the invention, the universal device for coupling a computer bus to a controller of a group of peripherals connected to one another by a specific link to which the controller is physically connected, including:
a microprocessor associated with at least one memory containing its own operating system, PA1 an interface for linkage with the controller assuring the transfer of the useful data of the frames and control blocks containing the command characters relating to the constitution of frames transmitted either to the link or to the bus, PA1 is characterized in that it includes a double-port random-access buffer memory connected by way of a first bus to said interface and by way of a second bus to the computer bus via a specific interface of the computer, the transfer of the data between the linking interface and the double-port memory, on the one hand, between the latter and the computer bus on the other, being organized by the microprocessor, the latter transfer being effected under the control of a direct memory access circuit, and the conversion of the specific command characters of the protocols used on the computer bus into those used on the link and vice versa being performed by the microprocessor, which assures their transfer over its internal bus to or from the linking interface.